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RMBA19500
May 2004
RMBA19500
PCS 2 Watt Linear GaAs MMIC Power Amplifier
General Description
The RMBA19500 is a highly linear Power Amplifier. The circuit uses our pHEMT process. It has been designed for use as a driver stage for PCS base stations, or as the output stage for Micro- and Pico-Cell base stations. The amplifier has been optimized for high linearity requirements for CDMA operation.
Features
* 2 Watt Linear output power at 36dBc ACPR1 for CDMA operation * Small signal gain of 30dB typ. * Small outline SMD package
Device
Absolute Ratings
Symbol Vd Vg PRF TC TS Parameter Drain Supply Voltage1 Gate Supply Voltage RF Input Power (from 50 source) Operating Case Temperature Range Storage Temperature Range Ratings +10 -5 +5 -30 to +85 -40 to +100 Units V V dBm C C
Note: 1. Only under quiescent conditions--no RF applied.
(c)2003 Fairchild Semiconductor Corporation
RMBA19500 Rev. C
RMBA19500
Electrical Characteristics2
Parameter Frequency Range Gain (Small Signal) Over 1930-1990MHz Gain Variation: Over Frequency Range Over Temperature Range Noise Figure Linear Output Power: for CDMA3 OIP34 PAE @ 33dBm Pout Input VSWR (50) Drain Voltage (Vdd) Gate Voltage (VG1, 2 and VG3)5 Quiescent Currents (IDQ1, 2 and IDQ3)5 Thermal Resistance (Channel to Case) RJC Min 1930 Typ 30 1.0 1.5 6 33 43 24 2:1 7.0 -2 180, 445 11 -0.25 Max 1990 Units MHz dB dB dB dB dBm dBm % V V mA C/W
Notes: 2. VDD = 7.0V, TC = 25C. Part mounted on evaluation board with input and output matching to 50. 3. 9 Channel Forward Link QPSK Source; 1.23Mbps modulation rate. CDMA ACPR1 is measured using the ratio of the average power within the 1.23MHz channel at band center to the average power within a 30KHz bandwidth at an 885KHz offset. Minimum CDMA output power is met with ACPR1 > 36dBc. 4. OIP3 specifications are achieved for power output levels of 27 and 30dBm per tone with tone spacing of 1.25MHz at band-center with adjusted supply and bias conditions of Vdd = 6.5V and IdqTotal = 625mA (see Note 5). 5. VG1,2 and VG3 must be individually adjusted to achieve IDQ1,2 and IDQ3. A single VGG bias supply adjusted to achieve IDQTOTAL = 625mA can be used with nearly equivalent performance. Values for IDQ1,2 and IDQ3 shown have been optimized for CDMA operation. IDQ1, 2 and IDQ3 (or IDQTOTAL) can be adjusted to optimize the linearity of the amplifier for other modulation systems. The device requires external input and output matching to 50 as shown in Figure 3 and the Parts List.
(c)2003 Fairchild Semiconductor Corporation
RMBA19500 Rev. C
RMBA19500
Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE The following describes a procedure for evaluating the RMBA19500, a monolithic high efficiency power amplifier, in a surface mount package, designed for use as a driver stage for PCS Base station or as the final output stage for Micro- and Pico-Cell base stations. Figure 1 shows the package outline and the pin designations. Figure 2 shows the functional block diagram of the packaged product. The RMBA19500 requires external passive components for DC bias and RF input and output matching circuits. A recommended schematic circuit is shown in Figure 3. The gate biases for the three stages of the amplifier may be set by simple resistive voltage dividers. Figure 4 shows a typical layout of an evaluation board, corresponding to the schematic circuits of Figure 3. The following designations should be noted: (1) Pin designations are as shown in Figure 2. (2) Vg1, Vg2, and Vg3 are the Gate Voltages (negative) applied at the pins of the package. (3) Vgg1, Vgg2 and Vgg3 are the negative supply voltages at the evaluation board terminals (Vg1 and Vg2 are tied together). (4) Vd1, Vd2 and Vd3 are the Drain Voltages (positive) applied at the pins of the package. (5) Vdd is the positive supply voltage at the evaluation board terminal (Vd1, Vd2, and Vd3 are tied together). Note: The base of the package must be soldered on to a heat sink for proper operation.
Top View
0.200 SQ.
6 5 4
Bottom View
4 5 6
7
3 2
0.015
3 7 8 9 2 1
0.030
8
9
1
0.020 0.011
10 11 12
12 11 10
0.041
Plastic Lid
0.010
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13
Description RF Out & Vd3 RF Out & Vd3 RF Out & Vd3 VD1 GND VG1 RF In GND VG2 VD2 GND VG3 GND
0.075 MAX
0.230 0.246 0.282
Side Section
Dimensions in inches
Figure 1. 12 Lead Plastic Air Cavity Package with Integral Heat Sink
(c)2003 Fairchild Semiconductor Corporation
RMBA19500 Rev. C
RMBA19500
Vd1 Pin #4
Vd2 Pin #10
GND Pin #5, 8, 11, 13
MMIC CHIP
RF IN Pin #7
RF OUT & Vd3 Pin #1, 2, 3
Vg1 Pin #6
Vg 2 Pin # 9
Vg 3 Pin #12
Figure 2. Functional Block Diagram of Packaged Product
R4 30
R2 1k
R3 910
L1 5.6nH
C3 1500pF
RFIN
J1 C1 10pF R1 20 RMBA19500 L3 10nH C6 0.1F C5 1500pF R5 20 L2 5.6nH C7 0.1F C4 1500pF C8 0.1F C9 2.2pF
C2 10.0pF
RFOUT
J2
C10 2.2pF
P1 VG1, VG2
P3 GND
P4 VD1, 2, 3
P2
VGG3
Figure 3. Schematic of Application Circuit Showing External Components
(c)2003 Fairchild Semiconductor Corporation
RMBA19500 Rev. C
RMBA19500
Figure 4. Layout of Test Evaluation Board (RMBA19500-TD, G655971)
Test Procedure for the Evaluation Board (RMBA19500-TB)
CAUTION: LOSS OF GATE VOLTAGES (Vg1, Vg2, Vg3) WHILE CORRESPONDING DRAIN VOLTAGES (Vdd) ARE PRESENT CAN DAMAGE THE AMPLIFIER. The following sequence must be followed to properly test the amplifier. (It is necessary to add a fan to provide air cooling across the heat sink of RMBA19500.) Step 1: Turn off RF input power. Step 6: Follow turn-off sequence of: Step 2: Use GND terminal of the evaluation board for the ground of the DC supplies. Set Vgg1, Vgg2 and Vgg3 to -3V (pinch-off). Step 3: Slowly apply drain supply voltages of +7V to the board terminal Vdd ensuring that there is no short. (i) Turn off RF Input Power (ii) Turn down and off drain voltage Vdd. (iii) Turn down and off gate voltages Vgg1, Vgg 2 and Vgg3. Step 4: Adjust Vgg12 up from -3V until the drain current (with no RF applied) increases to Idq12 as per supplied result sheet. Then adjust Vgg3 until the total drain current becomes equal to the sum of Idq12 and Idq3. Step 5: After the bias condition is established, RF input signal may now be applied at the appropriate frequency band and appropriate power level.
(c)2003 Fairchild Semiconductor Corporation
RMBA19500 Rev. C
RMBA19500
Parts List for Test Evaluation Board (RMBA19500-TB, G6655917)
Part L1, L2, L4 L3 C1 C9 C3, C4, C5 C10 C2 C8, C11, C14, C15 C6, C7 R1, R5 R2, R7 R3 R4 R6 R8 R9 U1 HS P1 J1, J2 Board FR4 Value 5.6nH 10nH 10pF 2.2pF 1500pF 2.0pF 15.0pF 4.7F 0.1F 20 1000 910 30 1.1K 390 300 RMBA19500 Heatsink Terminals SMA Connectors Size (EIA) .06" x .03" .085" x .060" .067" x .036" .042" x .022" .067" x .036" .042" x .022" .134" x .071" .183" x .054" .069" x .037" .069" x .037" .069" x .037" .069" x .037" .069" x .037" Vendor(s) Toko (LL1608-F5N6) Coilcraft (0805HT-10NTKBC) Murata (GRM39COG100J050AD) Murata (GRM36COG2R2J050BD) Murata (GRM39Y5V152Z50V) Murata (GRM36COG2R20J050BD) Murata (GRM36COG150J050) TDK (C3216XR1A475KT) Murata (GRM39Y5V104Z50) IMS (RCI-0603-20R0J) IMS (RCI-0603-1001J) IMS (RCI-0603-9100J) IMS (RCI-0603-30R0J) IMS (RCI-0603-1101J) IMS (RCI-0603-3900J) IMS (RCI-0603-3000J) Fairchild Fairchild, G655548 3M (2340-5211TN) E.F. Johnson (142-0701-841) Fairchild Dwg# G654187/G654941
.31" x .41"
Thermal Considerations for Heat Sinking the RMBA19500
The PWB must be prepared with either an embedded copper slug in the board where the package is to be mounted or a heat sink should be attached to the backside of the PWB where the package is to be mounted on the front side. The slug or the heat sink should be made of a highly electrically and thermally conductive material such as copper or aluminum. The slug should be at least the same thickness as the PWB. In the case of the heat sink, a small pedestal should protrude through a hole in the PWB where the package bottom is directly soldered. In either configuration, the top surface of the slug or the pedestal should be made coplanar with the package lead mounting plane i.e., the top surface of the PWB. Use Sn96 solder (96.5% Sn and 3.5% Ag) at 220C for 20 seconds or less to attach the heat sink to the backside of the PWB. Then, using Sn63, the package bottom should be firmly soldered to the slug or the pedestal while the pins are soldered to the respective pads on the front side of the PWB without causing any stress on the pins. Remove flux completely if used for soldering.
(c)2003 Fairchild Semiconductor Corporation
RMBA19500 Rev. C
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
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DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I11

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